As is well known, solid state storage devices such as SD cards or solid state drives (SSD) are widely used in a variety of electronic devices.
Generally, a solid state storage device comprises a non-volatile memory. After data are written to the non-volatile memory, if no electric power is supplied to the solid state storage device, the data are still retained in the non-volatile memory. A flash memory is one of the widely-used non-volatile memories. In addition, a NAND-based flash memory is the non-volatile memory with the largest capacity.
FIG. 1 is a schematic functional block diagram illustrating the architecture of a conventional solid state storage device. As shown in FIG. 1, the solid state storage device 10 comprises an interface controller 101 and a non-volatile memory 105. The non-volatile memory 105 further comprises a memory cell array 109 and an array control circuit 111.
The solid state storage device 10 is connected with a host 14 through an external bus 12. For example, the external bus 12 is an USB bus, a SATA bus, a PCIe bus, a M.2 bus, an U.2 bus, or the like.
Moreover, the interface controller 101 is connected with the non-volatile memory 105 through an internal bus 113. According to a write command from the host 14, the interface controller 101 controls the array control circuit 111 to store the write data from the host 14 to the memory cell array 109. Alternatively, according to a read command from the host 14, the interface controller 101 controls the array control circuit 111 to acquire a read data from the memory cell array 109. In addition, the read data is transmitted to the host 14 through the interface controller 101.
Generally, the interface controller 101 stores a default read voltage set. During a read cycle, the interface controller 101 transmits an operation command to the array control circuit 111 of the non-volatile memory 105 through the internal bus 113. Consequently, the interface controller 101 allows the array control circuit 111 to read the previously-stored data from the memory cell array 109 of the non-volatile memory 105 according to the default read voltage set.
The interface controller 101 further comprises an error correction (ECC) unit 104 for correcting the error bits of the read data. After the error bits of the read data are corrected, the accurate read data is transmitted to the host 14. The operating principles will be described as follows.
Depending on the amount of the data to be stored in the memory cell, the memory cells may be classified into four types, i.e. a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC) and a quad-level cell (QLC). The SLC can store only one bit of data per cell. The MLC can store two bits of data per cell. The TLC can store three bits of data per cell. The QLC can store four bits of data per cell. In other words, the memory cell array 109 is a SLC memory cell array, a MLC memory cell array, a TLC memory cell array or a QLC memory cell array.
In the memory cell array 109, each memory cell comprises a floating gate transistor. By adjusting the number of hot carriers injected into a floating gate of the floating gate transistor, the array control circuit 111 controls the storing state of the floating gate transistor. In other words, the floating gate transistor of each SLC has two storing states, the floating gate transistor of each MLC has four storing states, the floating gate transistor of each TLC has eight storing states, and the floating gate transistor of each QLC has sixteen storing states.
FIG. 2 schematically illustrates the ideal threshold voltage distribution curves of triple-level cells in different storing states. According to the number of injected hot carriers, the triple-level cell has eight storing states “Erase” and “A” ˜“G”. Before the hot carriers are injected into the memory cell, the memory cell is in the storing state “Erase”. After the hot carriers are injected into the memory cell, the memory cell is in the storing state “A”. As the number of the injected hot carriers increases, the memory cell is sequentially in the other seven storing states “A” ˜“G”. For example, the memory cell in the storing state “G” has the highest threshold voltage, and the memory cell in the storing state “Erase” has the lowest threshold voltage.
Please refer to FIG. 2. For example, the memory cell storing the data “111” is in the storage state “Erase”. The memory cell storing the data “011” is in the storage state “A”. The memory cell storing the data “001” is in the storage state “B”. The memory cell storing the data “101” is in the storage state “C”. The memory cell storing the data “100” is in the storage state “D”. The memory cell storing the data “000” is in the storage state “E”. The memory cell storing the data “010” is in the storage state “F”. The memory cell storing the data “110” is in the storage state “G”.
In practice, even if many memory cells are in the same storing state during the program cycle, the threshold voltages of these memory cells are not all identical. That is, the threshold voltages of these memory cells are distributed in a specified distribution curve with a median threshold voltage. The median threshold voltage of the memory cells in the storing state “Erase” is Ver. The median threshold voltage of the memory cells in the storing state “A” is Va. The median threshold voltage of the memory cells in the storing state “B” is Vb. The median threshold voltage of the memory cells in the storing state “C” is Vc. The median threshold voltage of the memory cells in the storing state “D” is Vd. The median threshold voltage of the memory cells in the storing state “E” is Ve. The median threshold voltage of the memory cells in the storing state “F” is Vf. The median threshold voltage of the memory cells in the storing state “G” is Vg. For example, the median threshold voltage for a greater number of memory cells in the storing state “A” is Va.
Please refer to FIG. 2 again. According to the above characteristics of the triple-level cell, a read voltage set including seven read voltages Vra˜Vrg is defined. During the read cycle, the array control circuit 111 provides the seven read voltages of the read voltage set Vra˜Vrg, in a predefined order, to the array control circuit 111 in order to detect the storing states of the triple-level cells in the memory cell array 109.
During the read cycle, the array control circuit 111 has to perform at least three read steps to judge the storing state of the triple-level cell. An example of judging the storing state “C” of the triple-level cell will be described as follows.
In the first read step, the array control circuit 111 provides the read voltage Vrd to the memory cell array 109. If the threshold voltage of the memory cell is lower than the read voltage Vrd and the memory cell is turned on, the array control circuit 111 judges that the memory cell is in the storing state “Erase”, “A”, “B” or “C”. Whereas, if the threshold voltage of the memory cell is higher than the read voltage Vrd and the memory cell is turned off, the array control circuit 111 judges that the memory cell is in the storing state “D”, “E”, “F” or “G”.
In the second read step, the array control circuit 111 provides the read voltage Vrb to the memory cell array 109. If the threshold voltage of the memory cell is higher than the read voltage Vrb and the memory cell is turned off, the array control circuit 111 judges that the memory cell is in the storing state “B” or “C”. Whereas, if the threshold voltage of the memory cell is lower than the read voltage Vrb and the memory cell is turned on, the array control circuit 111 judges that the memory cell is in the storing state “Erase” or “A”.
In the third read step, the array control circuit 111 provides the read voltage Vrc to the memory cell array 109. If the threshold voltage of the memory cell is higher than the read voltage Vrc and the memory cell is turned off, the array control circuit 111 judges that the memory cell is in the storing state “C”. Whereas, if the threshold voltage of the memory cell is lower than the read voltage Vrc and the memory cell is turned on, the array control circuit 111 judges that the memory cell is in the storing state “B”.
As mentioned above, the storing state of the triple-level cell is determined according to the seven read voltages Vra˜Vrg of the read voltage set. In the three read steps of the read cycle, three read voltages of the seven read voltages Vra˜Vrg are selected to determine the storing state of the triple-level cell.
Similarly, the default read voltage set for the single-level cell includes one read voltage. After one read step is performed, the two storing states of the single-level cells are determined according to the read voltage of the default read voltage set.
Similarly, the default read voltage set for the multi-level cell includes three read voltages. After two read steps are performed, the four storing states of the multi-level cells are determined according to three read voltages of the default read voltage set.
Similarly, the default read voltage set for the quad-level cell includes fifteen read voltages. After four read steps are performed, the sixteen storing states of the quad-level cells are determined according to fifteen read voltages of the default read voltage set.
Moreover, the interface controller 101 erases the contents of the non-volatile memory 105 in a block-wise fashion. When the interface controller 101 intends to erase the contents of a selected block of the memory cell array 109, an erase command corresponding to the selected block is transmitted from the interface controller 101 to the non-volatile memory 105.
After an erase cycle, all memory cells in the selected block of the memory cell array 109 are restored to the storing state “Erase”. In the storing state “Erase”, no hot carriers are injected into the memory cell.
For verifying whether all memory cells of the selected block are restored to the storing state “Erase”, an incremental step pulse erase (ISPE) technology has been disclosed. The array control circuit 111 uses the ISPE technology to erase the contents of the selected block.
FIG. 3 is a schematic timing waveform diagram illustrating the associated voltages processed by the ISPE technology. By using the ISPE technology, the memory cells in the selected block of the memory cell array 109 are restored to the storing state “Erase” according to a pulse signal. The erase cycle comprises plural erase steps. Each erase step contains an erase pulse period and a verification period.
The period between the time point to and the time point tb is an erase pulse period (Te1) of the first erase step. In the erase pulse period Te1, the erase pules with an amplitude Vp1 is provided from the array control circuit 111 to the memory cell array 109 to erase the contents of all memory cells in the selected block.
The period between the time point tb and the time point tc is an erase verification period (Tv1) of the first erase step. In the erase verification period Tv1, a verification pules is provided from the array control circuit 111 to the memory cell array 109. According to the output current from the selected block, the array control circuit 111 verifies whether the erase operation is successful. If the array control circuit 111 verifies that the erase operation is not successful, the second erase step is continuously performed.
The period between the time point tc and the time point td is an erase pulse period (Te2) of the second erase step. In the erase pulse period Te2, the erase pules with an amplitude Vp2 is provided from the array control circuit 111 to the memory cell array 109 to erase the contents of all memory cells in the selected block. The amplitude Vp2 is higher than the amplitude Vp1.
The period between the time point td and the time point te is an erase verification period (Tv2) of the second erase step. In the erase verification period Tv2, a verification pules is provided from the array control circuit 111 to the memory cell array 109. According to the output current from the selected block, the array control circuit 111 verifies whether the erase operation is successful. If the array control circuit 111 verifies that the erase operation is not successful, the third erase step is continuously performed.
The period between the time point te and the time point tf is an erase pulse period (Te3) of the third erase step. In the erase pulse period Te3, the erase pules with an amplitude Vp3 is provided from the array control circuit 111 to the memory cell array 109 to erase the contents of all memory cells in the selected block. The amplitude Vp3 is higher than the amplitude Vp2.
The period between the time point tf and the time point tg is an erase verification period (Tv3) of the third erase step. In the erase verification period Tv3, a verification pules is provided from the array control circuit 111 to the memory cell array 109. According to the output current from the selected block, the array control circuit 111 verifies whether the erase operation is successful. If the array control circuit 111 verifies that the erase operation is successful, the erase cycle is ended.
As mentioned above, the array control circuit 111 performs at least one erase step during the erase cycle. If the array control circuit 111 verifies that the selected block has not been successfully erased, the erase pules with the higher amplitude is provided from the array control circuit 111 to the memory cell array 109. Moreover, the next erase step is performed until the array control circuit 111 verifies that the selected block has been successfully erased. As shown in FIG. 3, the array control circuit 111 verifies that the selected block has been successfully erased after three erase steps of the erase cycle.
After the array control circuit 111 verifies that the selected block has been successfully erased, the array control circuit 111 issues an erase pass message to the interface controller 101. According to the erase pass message, the selected block is recorded as a blank block by the interface controller 101. In the subsequent program cycle, the write data from the host 14 can be stored in the blank block.
With increasing development of the semiconductor manufacturing process, the structure of the memory cell array becomes more complicated and the capacity of the memory cell array is gradually increased. Consequently, the solid state storage device with the 2D NAND flash memory is gradually replaced by the solid state storage device with the 3D NAND flash memory.
However, the above verification method still has some drawbacks. After the erase command is transmitted from the interface controller 101 to the non-volatile memory 105 and the array control circuit 111 verifies that the selected block has been successfully erased, the array control circuit 111 issues the erase pass message to the interface controller 101. However, in practice, some memory cells of the selected block are still not restored to the storing state “Erase”.
If such fake-erased block is used for storing the write data from the host, many error bits will be generated during the read cycle. Moreover, if the fake-erased block contains too many error bits, the ECC circuit 104 of the interface controller 101 cannot correct the error bits. Under this circumstance, a read failure problem occurs.